The 1900 Range – Index

1 - 1900 Architecture and System Description

1.1 - How the ICT 1900 Series evolved

1.2 - The ICT 1900 Range in 1966

1.3 - ICT 1900 Range Architecture

1.3.1 - System Architecture

1.3.2 - Standard Interface

1.3.3 - 1900 Executive

1.3.4 - The 1900 Range Order Code

1.3.5 - FP6000 Processor Data Flow

1.3.6 - Span of the Range

1.4 - Hardware technology in the ICT/ICL 1900 Range

2 - 1900 Performance and Competitive Position

2.1 - 1900 at the start- FP 6000 performance

2.2 - Performance of ICT 1900 in 1966

2.3 - Performance of ICT / ICL 1900 Series (All Models) and 2903/ME29

2.4 - ICT 1900 competitive position

3 - 1900 Software

3.1 - The FP 6000 Software (Before the 1900 Range)

3.2 - ICT 1900 Range Software - The Start

3.3 - Programming Aids (Software) in 1966

3.4 - The Operating Systems (George).

3.5 - ICT/ICL 1900 Software - Two views from the Board

3.6 - ICT/ICL 1900 Software in 1972

4 - 1900 Range in the Market

4.1 - 1900 Road Map

4.2 - Approx. Quantities delivered.

4.3. - Customers list and Applications

4.3.1 - The 1900 Users Group

4.3.2 - Some Customers Details

5 - 1900 Acknowledgements and References

Comments received

Virgilio Pasqoali

2.2- Performance of ICT 1900 in 1966

This table, extracted from an ICT document (November 1966), gives to prospective customers some key figures for each member of the ICT 1900 Range.

Performance figures are the major part of its contents.

The performance of small scientific loops is included in the table. An assessment of the relative power of each relevant model of the range in the execution of this type of work is also included.

I.C.T. 1900 Series (in 1966)

Characteristics of central processors

		1901	1902	1903	1904	1905	1906	1907
Core store cycle time (micro-seconds)		6	6	1.8 or 2	2	2	1.1 or 2.1 up to 1.25 or 2.25 for largest core store	1.1 or 2.1 up to 1.25 or 2.25
Data channels (maxima)	general	3/6	8	8	18	18	18	18
	fast	—	—	—	5	5	any number as required

		1901	1902	1903	1904	1905	1906	1907
Arithmetic times:							(At 1.25 µS cycle time)
Fixed point	add/subtract	34 µS	18 µS	7 µS	7 µS	7 µS	2.5 µs	2.5 µS
	multiply	4.7 ms	1.5ms	650 µS	40 µS	40 µS	10.05 µS	10.05 µS
	divide	7 ms	2.3 ms	900 µS	44 µS	44 µS	18 µS	18 µS
	jump	21 µS	13 µS	5 µS	5 µS	5 µS	2.5 µS	2.5 µS
Floating point	add/subtract	Floating point arithmetic is available				13 µS	185 µS	4 to 7.25 µS†
	load					6 µS	115 µS	0.5 to 2.5 µS†
	store					8 µS	110 µS	1.25 to 2.5 µS†
	multiply					29 µS	290 µS	10 to 13.25µS†
Address modification‡						2 µS	625 µS	0.625 µS
Scalar product loop x' = x + a;b;						60 µS	700 µS	24.2 µS
Polynomial loop x' = x (x + a;)						42 µS	480 µS	16 µS
Approximate agreed ratio for performing typical scientific calculations based on the above polynomial loop			1	2-5	11	250	22	650
Number of time-shared programs		1	1	1	4	4	16	16
each with sub-programs			2	2	2	2	3	3

Word length: Fixed point: 24 binary digits—four alpha-numeric characters.

Floating point: Argument 37 bits plus sign. Exponent 8 bits plus sign.

‡1905 and 1907 processors incorporate floating point unit. Address modification of most floating point instructions takes no extra time due to overlapping of instructions.

†According to context

This specification is subject to modification