The 1900 Range – Index

1 - 1900 Architecture and System Description

1.1 - How the ICT 1900 Series evolved

1.2 - The ICT 1900 Range in 1966

1.3 - ICT 1900 Range Architecture

1.3.1 - System Architecture

1.3.2 - Standard Interface

1.3.3 - 1900 Executive

1.3.4 - The 1900 Range Order Code

1.3.5 - FP6000 Processor Data Flow

1.3.6 - Span of the Range

1.4 - Hardware technology in the ICT/ICL 1900 Range

2 - 1900 Performance and Competitive Position

2.1 - 1900 at the start- FP 6000 performance

2.2 - Performance of ICT 1900 in 1966

2.3 - Performance of ICT / ICL 1900 Series (All Models) and 2903/ME29

2.4 - ICT 1900 competitive position

3 - 1900 Software

3.1 - The FP 6000 Software (Before the 1900 Range)

3.2 - ICT 1900 Range Software - The Start

3.3 - Programming Aids (Software) in 1966

3.4 - The Operating Systems (George).

3.5 - ICT/ICL 1900 Software - Two views from the Board

3.6 - ICT/ICL 1900 Software in 1972

4 - 1900 Range in the Market

4.1 - 1900 Road Map

4.2 - Approx. Quantities delivered.

4.3. - Customers list and Applications

4.3.1 - The 1900 Users Group

4.3.2 - Some Customers Details

5 - 1900 Acknowledgements and References

Comments received

Virgilio Pasqoali

1.3.5 – FP6000 Processor Data Flow

This extract from the April 1963 visit report details the dataflow of the FP6000 processor being recommended for adoption. It later became the ICT 1904.

Data Flow

General – The above figure shows the main FP6000 data flow which is relatively straightforward. One unusual feature is the dumping of the order number register P into store during all double length operations (including multiply, divide and floating point).

Briefly the data flow consists of a mill (+, &, ≠) with 2, 24 bit parallel input highways and one 24 bit output highway. The latter emerges via a shift facility (0, +1,-1). The accumulators are not external but held in the core store. The L input highway serves A, a 24 bit working register with output complementing facility for subtraction, D, a 9 bit register holding the datum for that programme (see time sharing below). The K input highway serves B, the core store data register, P, the order number register which is also used for double length numbers and N, a 15 bit register holding the store address. P has a shifting facility (+1,-1) for use in multiplication and division.

Store addressing and data

The store is addressed for instructions, operands (N), accumulators (X) and modifiers (M) all relative to the datum D for that programme which is added to all N addresses but ORed to X and M (See below). A further facility is provided for addressing the store with X+1 for double length quantities. Data into and out of the store is via the B register which is actually the store data register. The latter is not part of the memory as is usual. This assists considerably in simplifying store expansion. Similarly, N, is the store address register. All data transfers to and from store are checked by a 24 bit parity generator/ checker which also checks peripheral transfers over the standard interface.

Multiprogramming (Time Sharing)

A hardware facility provides a reservation check that the address N (modified by M if required) is less than or equal to L and adds the datum B to N. This ensures that all store accesses lie between D and D+L. D and L are set by the EXECUTIVE (Supervisor). Both D and L are modulo 64.